To ensure proper functionality and reliability, integrated circuits (ICs) are generally tested before shipping or placing the ICs in final products. Integrated circuits are commonly tested on automated test equipment (ATE), such as the Verigy 93000 SOC Tester.
FIG. 1 shows a typical SOC Tester 100, comprising a test head 110; a device under test (DUT) interface 120; a manipulator 130; a DUT board 150; a support rack 140; cables and hoses 160 between test head 110 and support rack 140; user interface 170 connected to support rack 140 with interconnect 144; optional off rack test program storage 180 connected to user interface 170 and support rack 140 with interconnect 142. There may also be a cooling unit (not shown) connected to the test head 110 for cooling hardware internal to the test head 110, probers (not shown) and handlers (not shown).
DUT interface 120 provides docking capabilities to handlers and wafer probers (not shown). The docking mechanism may be controlled by compressed air or mechanically, but if required may also be operated manually. Test head 110 is usually a water-cooled system and receives its cooling water supply from support rack 140 via hoses and cables 160, which in turn is connected by two flexible hoses to the cooling unit (not shown).
Support rack 140 houses a system controller (not shown), which is typically a Linux controller. Support rack 140 is attached to the manipulator 130 and serves as the interface between test head 110 and any of the following: an AC power source; water cooling source; compressed air source; the user interface; the off rack test program storage and other system management means. Tester 100 may also comprise additional support racks such as analog support racks for installing additional analog instruments. Manipulator 130 supports and positions test head 110 and provides 6 degrees of freedom for precise and repeatable connections between test head 100 and handlers or wafer probers (not shown).
Test head 110 comprises tester electronics and additional analog modules. With current technology, test head 110 may be configured with 512 pins or 1024 pins, but this will likely increase in the future. A 512 pin test head comprises 4 card cages (not shown) while a 1024 pin test head comprises 8 card cages (not shown). Each card cage may contain 8 test cards, respectively. A single test card supports 16 pins, making 128 pins per cage. Thus, a 4 cage test head contain 512 pins and an 8 cage test head 1024 pins. During testing, a DUT is mounted on a contactor (not shown) on the DUT board 150, which is connected to I/O channels by DUT interface 120. DUT interface 120 may comprise high performance coax cabling and spring contact pins or pogo pins, which establish electrical connection with DUT board 120.
FIGS. 2 and 3 show a test card 200 that may be housed within one of the 4 or 8 card cages 310, 312, 314, 316 of test head 110. Referring now specifically to FIG. 2, test card 200 may contain memory 210, a test processor 220, electronics 230, signal routing 240, pin routing 250, among other necessary circuitry and components. As will be appreciated by those skilled in the art, various test cards 200 are mounted in card cages 310, 312, 314, 316 of test head 110. Test cards 200 support testing of devices under test by generating waveforms or electrical signals that provide input to a device. The test card can also receive signals and measurement data to determine whether the device passed or failed.
During testing, an end user may interface with the tester 100 via the user interface 170. The end user may instruct the tester 100 to load a test program and run a test. The tester 100 can not run a test until the test program has been loaded. A test program may contain information about the device under test, including pins and specifications by which to test the device. A test program is generally saved to disk, but may be saved in disk memory on rack 140 or off rack 180 in a test program storage unit, CD, tape or on a network.
This process generally involves reading the test program from the disk memory or other memory storage location, transferring the test program to the tester by wire (e.g., optical, network or other known link) and loading the test program into the appropriate memory locations in the hardware, which are typically the memory 210 on each test card 200 in each card cage 310, 312, 314, 316 in the test head 110, in order to provide test program instructions to each test processor for the pins controlled by each test card.
This process can take upwards of several hours, depending on the size of the test programs and associated data being down loaded. Current times for large test program files is 2-4 hours, but one can imagine that this will only increase with more complex and densely populated devices to test and more complex test programs and as the pin density of test cards is increased.
Thus, it will be appreciated that test program down load times will only increase using current test program downloading techniques. It will also be appreciated by those skilled in the art, that overall test time, which currently includes test program load time, is costly and a critical parameter that IC manufacturers are generally trying to decrease. The load time associated with loading a test program to tester hardware resources is especially critical if the operating system or the test software crash, as the test programs would have to be reloaded into the hardware resources on the tester. It would be advantageous if an SOC tester were able to load test programs to hardware resources on the tester more efficiently than current techniques permit.